--*********************************************
-- File: fewgates.vhd
--Name:
--Date:
--Lab Partner:
--*********************************************
--
-- This file has two errors in it -- fix them!
-- 
--Defining the library packages to be used


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--Declaration of the module's inputs and outputs
entity fewgates is port (

A: in std_logic;
B: in std_logic;
C: in std_logic;
Y: out std_logic

); 
end fewgates;

--Defining the modules behavior
Architecture behavioral of fewgates is 
begin
process (A, B, C) begin 

Y = C + ((NOT A) AND (NOT B));

end process;
end behavioral;