--*********************************************
-- File: fewgates_tb.vhd
--
-- Purpose: This file is used to test the fewgates VHDL code. 
-- It uses three inputs and one output.
--*********************************************
--Defining the library packages to be used
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

--Declaration of ModelSim libraries use
--INTERNET STUDENTS ***using Modelsim XE comment out the next two lines.
--Regular lab students leave them as is. 


LIBRARY UNISIM;
LIBRARY XILINXCORELIB;


ENTITY testbench IS
END testbench;

ARCHITECTURE testbench_arch OF testbench IS

COMPONENT fewgates
PORT (

a : in std_logic;
b : in std_logic;
c : in std_logic;
y : out std_logic

);
END COMPONENT;

SIGNAL a : std_logic;
SIGNAL b : std_logic;
SIGNAL c : std_logic;
SIGNAL y : std_logic;

--Defining the variable "CLK_PERIOD" to be equal to 50 nano seconds
constant CLK_PERIOD : time:= 50 ns;

BEGIN
--Unit under test is the module nand. Notice that it is not case sensitive
UUT : fewgates
--Defining external interface signals. This associates ports of the named entity with
--signals in the current architecture.
PORT MAP (

a => a,
b => b,
c => c,
y => y



);

signal_a_and_b_and_c: process
begin

a <= '0';	 b <= '0'; c <= '0';
wait for CLK_PERIOD;
a <= '0';	 b <= '1'; c <= '1';
wait for CLK_PERIOD;
a <= '1';	 b <= '0'; c <= '0';
wait for CLK_PERIOD;
a <= '1';	 b <= '1'; c <= '1';
wait for CLK_PERIOD;
a <= '0';	 b <= '0'; c <= '0';
wait for CLK_PERIOD;
a <= '0';	 b <= '1'; c <= '1';
wait for CLK_PERIOD;
a <= '1';	 b <= '0'; c <= '0';
wait for CLK_PERIOD;
a <= '1';	 b <= '1'; c <= '1';
wait for CLK_PERIOD;

end process;


END testbench_arch;