library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff_c is
  port (
    d, clk, clr : in std_logic;
    q : out std_logic);
end dff_c;

architecture Behavioral of dff_c is
begin

  process(clk)
    begin
      if (clk = '1' and clk'event) then
        if (clr = '1') then
          q <= '0';
        else
          q <= d;
        end if;
      end if;
  end process;

end Behavioral;