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VLSI Design Lab

 

        Journal Publications:
 

  1. P. Zarkesh-Ha, J.A. Davis, and J.D. Meindl, “Prediction of Net-Length Distribution for Global Interconnects in a Heterogeneous System-on-a-Chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, pp. 649–659, Dec. 2000.
  2. Q. Chen, J.A. Davis, P. Zarkesh-Ha, and J.D. Meindl, “A Compact Physical via Blockage Model,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, pp. 689–692, Dec. 2000.
  3. J. Joyner, R. Venkastesan, P. Zarkesh-Ha, J.A. Davis, and J.D. Meindl, “Impact of Three-Dimensional Architectures on Interconnects in Gigascale Integration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, pp. 922–928, Dec. 2001.
  4. J. D. Meindl, J. Davis, P. Zarkesh-Ha, C.S. Patel, K Martin, and P.A. Kohl, “Interconnect Opportunities for Gigascale Integration,” IBM Journal of Research and Development, vol. 46, pp. 245–263, May 2002.
  5. J. Joyner, P. Zarkesh-Ha, and J.D. Meindl, “Global Interconnect Design in a Three-Dimensional System-on-a-Chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, pp. 367–372, April 2004.
  6. P. Zarkesh-Ha and K. Doniger, “Interconnect Layout Sensitivity and Yield Prediction,” Electronic Device Failure Analysis Magazine, pp. 6-13, Feb. 2007.
  7. R. Ghaida and P. Zarkesh-Ha, “A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects,” Journal of Electronic Testing, Springer, July 2008.
  8. R. Ghaida, K Doniger, and P. Zarkesh-Ha, “Random Yield Prediction Based on a Stochastic Layout Sensitivity Model,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, issue 3, pp. 329-337, August 2009.
  9. P. Zarkesh-Ha and A. Shahi, “Stochastic Analysis and Design Guidelines for CNFETs in Gigascale Integrated Systems,” IEEE Transactions on Electron Devices, vol. 58, issue 2, pp. 530-539, Fe
  10. W. Y. Jang, M. Hayat, S. Godoy, S. Bender, P. Zarkesh-Ha, and S. Krishna, “Data Compressive Paradigm for Multispectral Sensing using Tunable DWELL Mid-infrared Detectors,” Optics Express, vol. 19, issue 20, pp. 19454–19472, September 2011.
  11. W-Y Jang, M. M. Hayat, P. Zarkesh-Ha, and S. Krishna, “Continuous time-varying biasing approach for spectrally tunable infrared detectors,” Optics Express, vol. 20, no. 28, pp. 29823-29836, 2012.
  12. A. Atghiaee, N. Masoumi, P. Zarkesh-Ha, and M. Mehri, “Predictive Application of PIDF and PPC for Interconnects Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, no.2, pp.438-443, Feb. 2014.
  13. M. M. Hayat, P. Zarkesh-Ha, G. El-Howayek, R. Efroymson, and J. C. Campbell, “Breaking the Buildup-Time Limit of Sensitivity in Avalanche Photodiodes by Dynamic Biasing,'' Optics Express, vol. 23, no. 18, pp. 24035-24041, Sept. 4, 2015.
  14. A. Neumann, J. Ghasemi, S. Nezhadbadeh, X. Nie, P. Zarkesh-Ha, and S. R. J. Brueck, "A CMOS-Compatible Plenoptic Detector for LED Lighting Applications", Optics Express, Sept. 7, 2015.
  15. G. R. C. Fiorante, J. Ghasemi, P. Zarkesh-Ha and S. Krishna, “Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing,” IEEE Transactions on Circuits and Systems I:, vol. 63, no. 11, pp. 1825-1832, Nov. 2016.
  16. B. Fahs , J. Chellis, M. Senneca, A. Chowdhury, S. Ray, A. Mirvakili, B. Mazzara, Y. Zhang, J. Ghasemi, Y. Miao, P. Zarkesh-Ha, V. Koomson, and M. Hella, “A 6-m OOK VLC Link Using CMOS-Compatible p-n Photodiode and Red LED,” IEEE Photonics Technology Letters, vol. 28, no. 24, pp. 2846-2849, Dec. 2016.
  17. J. Ghasemi, M. Bhattarai, G. Fiorante, P. Zarkesh-Ha, S. Krishna, and M. Hayat, "CMOS approach to compressed-domain image acquisition," Optics Express, vol. 25, issue 4, pp. 4076-4096, Feb. 2017.
  18. B. Fahs, A. Chowdhury, Y. Zhang, J. Ghasemi, C. Hitchcock, P. Zarkesh-Ha, M. Hella., “Design and Modeling of Blue-Enhanced and Bandwidth-Extended PN Photodiode in Standard CMOS Technology,” IEEE Transactions on Electron Devices, vol. 64, no. 7, pp. 2859-2866, July 2017.
  19. P. Dey and P. Zarkesh-Ha, “Effects of Device Parameter Variation in Low-Voltage Digital and Analog Circuits”, European Journal of Advances in Engineering and Technology (EJAET), Vol 4 Issue 11, pp. 788-796, Nov. 2017.
  20. A. Aslam, K. Hayat, A. Umar, B. Zohuri, P. Zarkesh-Ha, D. Modissette, S. Khan, and B. Hussian, “Wavelet-based convolutional neural networks for gender classification,” Journal of Electronic Imaging, SPIE, 28(1): 013012, Jan. 2019.               
  21. N. Sule, Z. Abedi, E. Schamiloglu, S. Hemmady, and P. Zarkesh-Ha, “Predictive Modeling of Non-Persistent Effects in MOSFET Response under Large Signal Gate Injection”, IEEE Transactions on Electromagnetic Compatibility, under review, as of Sept. 2019.

Conference Publications:
 
 

  1. P. Zarkesh-Ha and J.D. Meindl, “Stochastic Net-Length Distributions for Global Interconnects in a Heterogeneous System-on-a-Chip,” IEEE Symposium on VLSI Technology, pp. 44–45, June 1998.
  2. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, “On a Pin versus Gate Relationship for Heterogeneous Systems: Heterogeneous Rent’s Rule,” IEEE Custom Integrated Circuit Conference, pp. 93–96, May 1998.
  3. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, “Stochastic Interconnect Network Fan-out Distribution Using Rent’s Rule,” IEEE International Interconnect Technology Conference, pp. 184–186, June 1998.
  4. P. Zarkesh-Ha, T. Mule, and J.D. Meindl, “Characterization and Modeling of Clock Skew with Process Variations,” IEEE Custom Integrated Circuit Conference, pp. 441–444, May 1999.
  5. P. Zarkesh-Ha and J.D. Meindl, “Optimum Chip Clock Distribution Networks,” IEEE International Interconnect Technology Conference, pp. 18–20, May 1999.
  6. P. Zarkesh-Ha, P. Bendix, W. Loh, J. Lee, and J.D. Meindl, “The Impact of Cu/Low k on Chip Performance,” IEEE International ASIC/SoC Conference, pp. 257–261, Sep. 1999.
  7. P. Zarkesh-Ha and J.D. Meindl, “Asymptotically Zero Power Dissipation Gigahertz Clock Distribution Networks,” IEEE Electrical Performance and Electronic Packaging, pp. 57–60, Oct. 1999.
  8. P. Zarkesh-Ha and J.D. Meindl, “An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC),” IEEE Symposium on VLSI Technology, pp. 194–195, June 2000.
  9. P. Zarkesh-Ha, J.A. Davis, W. Loh, and J.D. Meindl, “Prediction of Interconnect Fan-out Distribution Using Rent’s Rule,” International Workshop on the System-Level Interconnect Prediction, pp. 107–112, April 2000.
  10. J. Joyner, P. Zarkesh-Ha, J.A. Davis, and J.D. Meindl, “A Three-Dimensional Stochastic Wire-Length Distribution for Variable Separation of Strata,” IEEE International Interconnect Technology Conference, pp. 126–128, June 2000.
  11. A. Naeemi, P. Zarkesh-Ha, C. Patel, and J.D. Meindl, “Performance Improvement using On-Board Wires for On-Chip Interconnects,” IEEE Electrical Performance and Electronic Packaging, pp. 325–328, Oct. 2000.
  12. P. Zarkesh-Ha and J.D. Meindl, “An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC),” Proceedings of the 12th International Conference on Microelectronics, pp. 149–152, Nov. 2000.
  13. Q. Chen, J.A. Davis, P. Zarkesh-Ha, and J.D. Meindl, “A Novel Via Blockage Model and Its Implications,” IEEE International Interconnect Technology Conference, pp. 15–17, June 2000.
  14. J. Joyner, P. Zarkesh-Ha, J.A. Davis, and J.D. Meindl, “Vertical Pitch Limitations on Performance Enhancement in Bonded Three-Dimensional Interconnect Architectures,” International Workshop on the System-Level Interconnect Prediction, pp. 123–127, April 2000.
  15. P. Zarkesh-Ha and J.D. Meindl, “An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC),” TECHCON’00, Sept. 2000.
  16. P. Zarkesh-Ha and J.D. Meindl, “Optimum On-Chip Power Distribution Networks for Gigascale Integration (GSI),” IEEE International Interconnect Technology Conference, pp. 125–127, June 2001.
  17. J. Joyner, P. Zarkesh-Ha, and J.D. Meindl, “A Global Interconnect Design Window for a Three-Dimensional System-on-a-Chip,” IEEE International Interconnect Technology Conference, pp. 154–156, June 2001.
  18. A. Naeemi, C. Patel, M. Bakir, P. Zarkesh-Ha, K. Martin, and J.D. Meindl, “Sea of Leads: a Disruptive Paradigm for System-on-a-Chip (SoC),” IEEE Solid State Circuit Conference, pp. 280–281, Feb. 2001.
  19. M. Saint-Laurent, P. Zarkesh-Ha, M. Swaminathan, and J.D. Meindl, “Optimal Clock Distribution with an Array of Phase-Locked Loops for Multiprocessor Chips,” Proceedings of the 44th IEEE Midwest Symposium on Circuits and Systems, pp. 127–131, August 2001.
  20. P. Zarkesh-Ha, W. Loh, P. Bendix, and J.D. Meindl, “Optimum Interconnect Design for ASIC Chips,” VLSI Multilevel Interconnection Conference (VMIC), pp. 407–412, Nov. 2001.
  21. J. Joyner, P. Zarkesh-Ha, and J.D. Meindl, “A Stochastic Global Net-Length Distribution for a Three-Dimensional system-on-a-Chip (3D-SoC),” IEEE International ASIC/SoC Conference, pp. 147–151, Sept. 2001.
  22. J. D. Meindl, R. Venkatesan, J. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. Bakir, T. Mule, P. Kohl, and K. Martin, “Interconnecting Device Opportunities for Gigascale Integration (GSI),” IEEE International Electron Device Meeting, pp. 525–528, Dec. 2001.
  23. P. Zarkesh-Ha, P. Wright, S. Lakshminarayanan, C-C Cheng, W. Loh, and W. Lynch, “Backend Process Optimization for 90nm High-Density ASIC Chips,” IEEE International Interconnect Technology Conference (IITC), pp. 123–125, June 2003.
  24. V. Sukharev, P. Zarkesh-Ha, C.H. Chang, W. Loh, and K. Zhang, “Metal Density Optimization With CMP-Based Dummy Placement,” International CMP Planarization for ULSI Multilevel Interconnection Conference (CMP-MIC), pp. 453–462, February 2003. (invited talk)
  25. P. Zarkesh-Ha, S. Lakshminarayann, K. Doniger, W. Loh, and P. Wright, “Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow,” International Symposium on Quality Electronic Design (ISQED), pp. 405–409, March 2003.
  26. P. Zarkesh-Ha, K. Doniger, W. Loh, and P. Wright, “Prediction of Interconnect Pattern Density Distribution: Derivation, Validation, and Applications,” International Workshop on the System-Level Interconnect Prediction (SLIP), pp. 85–91, April 2003.
  27. P. Zarkesh-Ha, P. Burke, K. Doniger, W. Loh, V. Sukharev, M. Lu, P. Bendix, W. Catabay, W.J. Hsia, and C.H. Chang, “Influence of Ultra Low k Dielectric on the Performance of Integrated Circuit Down to 45 nm Technology Node,” International VLSI/ULSI, Multilevel Interconnect Conference (VMIC), pp. 17–31, September 2003. (invited talk)
  28. P. Zarkesh-Ha, K. Doniger, W. Loh, D. Sun, R. Stephani, and G. Priebe, “A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors,” International Conference on Computer Design (ICCD), pp. 84–89, October 2003.
  29. P. Zarkesh-Ha, K. Doniger, W. Loh, and P. Bendix, "Prediction of Interconnect Adjacency Distribution, Validation, and Applications," International Workshop on the System Level Interconnect Prediction (SLIP), pp. 99-106, Feb. 2004.
  30. P. Zarkesh-Ha and K. Doniger, “Stochastic Interconnect Layout Sensitivity Model,” IEEE International Workshop on the System-Level Interconnect Prediction, pp. 9-14, March 2007.
  31. R. Sarvari, A. Naeemi, P. Zarkesh-Ha, and J. Meindl, “Design and Optimization for Nanoscale Power Distribution Networks in Gigascale Systems,” IEEE International Interconnect Technology Conference (IITC), pp. 190-192, June 2007.
  32. C. Hawkins, P. Zarkesh-Ha, J. Segura, “Little Vias can be Vicious,” 13th NASA Symposium on VLSI Design, June 2007.
  33. R. Abou Ghaida and P. Zarkesh-Ha, “Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 59-67, September 2007.
  34. V. Jain and P. Zarkesh-Ha, “Analytical Noise-Rejection Model Based on Short Channel MOSFET”, International Symposium on Quality Electronic Design (ISQED), pp. 401-406, March 2008.
  35. A. Mallajosyula and P. Zarkesh-Ha, “A Very Low Overhead Method to Filter Single Event Transients in Combinational Logic,” IEEE Workshop on Silicon Errors in Logic System Effects (SELSE), March 2008.
  36. A. Mallajosyula and P. Zarkesh-Ha, “A Robust Single Event Upset Hardened Clock Distribution Network,” IEEE International Integrated Reliability Workshop (IIRW), October 2008.
  37. S. Devarapalli, P. Zarkesh-Ha, and S. Suddarth, "Adaptive Circuit Implementation in FPGAs," FPGA Summit, Dec. 2008.
  38. V.S. Devarapalli, P. Zarkesh-Ha, and S. Suddarth, “Scavenger: An Adaptive Design Technique for Low Power ASIC/FPGA,” IEEE International Conference on Computing, Engineering, and Information, pp.164-167, April 2009.
  39. P. Zarkesh-Ha and A. Shahi, “Logic Gate Failure Characterization for Nanoelectronic EDA Tools,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 16-23, Oct. 2010.
  40. S. Devarapalli, P. Zarkesh-Ha, and S. Suddarth, “A robust and low power dual data rate (DDR) flip-flop using c-elements,” International Symposium on Quality Electronic Design (ISQED), pp. 147-150, March 2010.
  41. S. Devarapalli, P. Zarkesh-Ha, and S. Suddarth, “SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), pp. 167-171, Oct. 2010.
  42. A. Atghiaee, N. Masoumi, and P. Zarkesh-Ha, “Nano-scale Early-Design-Stage Prediction for Crosstalk-Induced Power,” International  Nanoelectronics Conference (INEC), pp. 585-586 , Jan. 2010.
  43. P. Zarkesh-Ha, W. Jang, P. Nguyen, A. Khoshakhlagh, and J. Xu, “A Reconfigurable ROIC for Integrated Infrared Spectral Sensing,” 23rd Annual Meeting of the IEEE Photonic Society, pp. 714-715, Nov. 2010.
  44. N. Purushotham, S. Devarapalli. J. Lyke, and P. Zarkesh-Ha, “Self-Healing Adjustable Memory System,” American Institute of Aeronautics and Astronautics, AIAA 2010-3373, April 2010.
  45. G. Bezerra, S. Forrest, M. Moses, A. Davis, and P. Zarkesh-Ha, “Modeling NoC Traffic Locality and Energy Consumption with Rent’s Communication Probability Distribution,” IEEE System Level Interconnect Prediction (SLIP) Workshop, pp. 3-8, June 2010.
  46. P. Zarkesh-Ha, G. Bezerra, S. Forrest, and M. Moses, “Hybrid Network on Chip (HNoC): Local Buses with a Global Mesh Architecture,” IEEE System Level Interconnect Prediction (SLIP) Workshop, pp. 9-14, June 2010.
  47. R. Helinski, T. LeBoeuf, C. Hoffman, and P. Zarkesh-Ha, “A Linear Digital VCO for Clock Data Recovery (CDR) Applications,” IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 98-101, Dec. 2010.
  48. P. Zarkesh-Ha, “A Novel LED/Detector Integrated Circuit,” World Scientific and Engineering Academy and Society (WSEAS) Conferences, March 2011. (invited talk)
  49. G. Bezerra, S. Forrest, and P. Zarkesh-Ha, “Reducing Energy and Increasing Performance with Traffic Optimization in Many-core Systems,” IEEE System Level Interconnect Prediction (SLIP) Workshop, June 2011.
  50. J. Xu, G. Fiorante, P. Zarkesh-Ha, and S. Krishna, “A Readout Integrated Circuit (ROIC) with Hybrid Source/Sensor Array,” to appear at the Annual Meeting of the IEEE Photonic Society, Oct. 2011.
  51. Ali Arabi Shahi, P. Zarkesh-Ha, “Prediction of gate delay variation for CNFET under CNT density variation,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp.140-145, Oct. 2012.
  52. Ali Arabi Shahi, P. Zarkesh-Ha, M. Elahi, “Comparison of variations in MOSFET versus CNFET in gigascale integrated systems,” 13th International Symposium on Quality Electronic Design (ISQED) pp.378-383, March 2012.
  53. Rogerio Cugler Fiorante, G.; Zarkesh-Ha, P.; Ghasemi, J.; Krishna, S., “Spatio-temporal tunable pixels for multi-spectral infrared imagers,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp.317-320, Aug. 2013.
  54. Ghasemi, J.; Zarkesh-Ha, P.; Fiorante, G.R.C.; Krishna, S., “A new CMOS readout circuit approach for multispectral imaging,” IEEE Photonics Conference (IPC), pp.592-593, Sept. 2013.
  55. P. Zarkesh-Ha, “Analysis of low-voltage mixed-signal circuits under device variations,” IEEE Faible Tension Faible Consommation (FTFC), vol., no., pp.1-4, June 2013.
  56. M. Hossain, J. Ghasemi, P. Zarkesh-Ha, and M. Hayat, “Design, modeling and fabrication of a CMOS compatible p-n junction avalanche photodiode,” IEEE Photonics Conference (IPC), pp. 584,585, Sept. 2013.
  57. M. Hossain, P. Zarkesh-Ha, J. David and M. Hayat, “Low breakdown voltage CMOS compatible p-n junction avalanche photodiode,” IEEE Photonics Conference (IPC), pp. 170-171, Oct. 2014.
  58. P. Zarkesh-Ha, “An intelligent readout circuit for infrared multispectral remote sensing,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 153-156, August 2014 (invited talk).
  59. J. West, S.  Imani, O. Lavrova, W. Cavanaugh, Jing Ju, K. Pupuhi, S. Keshavmurthy, J. Aarestad, and P. Zarkesh-Ha, “Reconfigurable power management using novel monolithically integrated CMOS-on-PV switch,” IEEE Photovoltaic Specialist Conference (PVSC),1389-1392, June 2014.
  60. J. Ghasemi, P. Zarkesh-Ha, S. Krishna, S. Godoy, M. Hayat, “A novel readout circuit for on-sensor multispectral classification,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 386-389, August 2014.
  61. M. Briggs, and P. Zarkesh-Ha, “Evaluating mobile SOCs as an energy efficient DSP platform,” IEEE International System-on-Chip Conference (SOCC), pp. 293-298, Sept. 2014.
  62. M. Uzzal, P. Zarkesh-Ha, J. Edwards, E. Coelho, and P. Rawat, “A highly sensitive ISFET using pH-to-current conversion for real-time DNA sequencing ,” IEEE International System-on-Chip Conference (SOCC), pp. 410-414, Sept. 2014.
  63. S. Ray, M. Hella, M. Hossain, P. Zarkesh-Ha, and M. Hayat, “Speed optimized large area avalanche photodetector in standard CMOS technology for visible light communication,” IEEE Sensors, pp. 2147-2150, Nov. 2014.
  64. P. Butala, H. Elgala, P. Zarkesh-Ha, and T. Little, “Multi-Wavelength Visible Light Communication System Design,” IEEE Workshop on Optical Wireless Communications (OWC’14), Dec. 2014.
  65. J. Ghasemi, A. Neumann, S. Nezhadbadeh, X. Nie, P. Zarkesh-Ha, and S. Brueck “A CMOS-Compatible Plenoptic Sensor for Smart Lighting Applications,” Conference on Lasers and Electro-Optics (CLEO), May 2015.
  66. F. Anwar, J. Nogan, P. Zarkesh-Ha, and M. Osinski, “Multilevel resistance in Ti/Pt/AlOx/HfOy/Ti/Pt/Ag resistive switching devices,” IEEE Nanotechnology Materials and Devices Conference (NMDC), pp. 1-3, Sept. 2015.
  67. M. Hossain, P. Zarkesh-Ha, and M Hayat, “Linear Mode CMOS Compatible p-n Junction Avalanche Photo diode With Operating Voltage Below 9V,” IEEE Photonics Conference (IPC), pp. 436-437, Oct. 2015.
  68. J. Ghasemi, A. Chowdhury, A. Neumann, B. Fahs, M. Hella, S. Brueck, and P. Zarkesh-Ha, “A Novel Blue-Enhanced Photodetector using Honeycomb Structure,” IEEE Sensors, pp. 1-3, Nov. 2015.
  69. P. Zarkesh-Ha, J. Edwards, and P. Szauter, “Avalanche ISFET: A Highly Sensitive pH sensor for Genome Sequencing,” IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 1-4, Oct. 2015.
  70. M. Uzzal, P. Zarkesh-Ha, P. Szauter, and J. Edwards, “Behavioral Modeling of Drain Current of an Avalanche ISFET near Breakdown Voltage,” to appear at the IEEE International System-on-Chip Conference (SOCC), Sept. 2016.
  71. M. Uzzal, P. Zarkesh-Ha, P. Szauter, and J. Edwards, “Analytical Noise Model for Avalanche ISFET Sensor Suitable for Next Generation Sequencing,” to appear at the IEEE International System-on-Chip Conference (SOCC), Sept. 2016.
  72. R. Mahto, P. Zarkesh-Ha and O. Lavrova, “MOSFET-Based Modeling and Simulation of Photovoltaics Module,” IEEE Photovoltaic Specialists Conference (PVSC), pp. 3078-3081, June 2016.
  73. R. Mahto, P. Zarkesh-Ha and O. Lavrova, “Reconfigurable Power Management for Monolithic CMOS-on-Photovoltaic under Partial and Complete Shading,” IEEE International Reliability Physics Symposium (IRPS), pp. 3C-4-1-3C-4-7, April 2016.
  74. B. Fahs, A. Chowdhury, Y. Zhang, J. Ghasemi, C. Hitchcock, P. Zarkesh-Ha, M. Hella, “Blue-Enhanced and Bandwidth-Extended Photodiode in Standard 0.35-um CMOS,” IEEE Sensors, pp. 1-3, Nov. 2016.
  75. M. Bhattarai, J. Ghasemi, G. Fiorante, P. Zarkesh-Ha, S. Krishna, and M. Hayat, “Intelligent Bias-Selection Method for Computational Imaging on a CMOS Imager,” IEEE Photonics Conference (IPC), pp. 244-245, Oct. 2016.
  76. R. Mahto, P. Zarkesh-Ha and O. Lavrova, “Reconfigurable Photovoltaic Integrated with CMOS for a Fault Tolerant System,” IEEE Photovoltaic Specialists Conference (PVSC), pp. 2578-2581, June 2016.
  77. A. T. Elshafiey, P. Zarkesh-Ha, and J. Trujillo, “The Effect of Power Supply Ramp Time on SRAM PUFs,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 946-949, August 2017.
  78. J. Soto, W. Valenzuela, S. Diaz, A. Saavedra, M. Figueroa, J. Ghasemi, P. Zarkesh-Ha, “An Intelligent Readout Integrated Circuit (iROIC) with On-Chip Local Gradient Operations,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 360-362, Dec. 2017.
  79. B. Fahs, A. J. Chowdhury, J. Ghasemi, P. Zarkesh-Ha and M. M. Hella, “A Robust 2×2 CMOS Receiver Array for Meter-Scale Point-to-Point OOK VLC links,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 663-666, August 2017.
  80. S. Nezhadbadeh, J. Ghasemi, A. Neumann, A. Chowdhury, B. Fahs, M. Hella, S. Brueck, and P. Zarkesh-Ha, “Characterization and Optimization of a Blue-Enhanced Honeycomb Optical Sensor," IEEE Sensors, pp. 1-3, Nov. 2017.
  81. E. Schamiloglu, S. Prasad, M. Fuks, S. Yurt, A. Elfrgani, K. Shipman, S. Hemmady, P. Zarkesh-Ha, Z. Peng, G. Balakrishnan, G. Heileman, Y. Shao, D. Dietz, “Recent Advances in High Power Microwave Sources and the Science of Electronics in Extreme Electromagnetic Environments at the University of New Mexico,” International Conference on Electromagnetics in Advanced Applications (ICEAA), pp. 622-625, Sept. 2017.
  82. B. Fahs, M. Senneca, J. Chellis, B. Mazzara, S. Ray, J. Ghasemi, Y. Miao, P. Zarkesh-Ha, V. Koomson, M. Hella, “A Meter-Scale 600-Mb/s 2×2 Imaging MIMO OOK VLC Link using Commercial LEDs and Si p-n Photodiode Array,” Wireless and Optical Communication Conference (WOCC), pp. 1-6, April 2017.
  83. A. Neumann, S. Nezhadbadeh, P. Zarkesh-Ha, and S. R. J. Brueck, "A CMOS-Compatible Plenoptic Sensor Array for Smart Lighting Applications," Advanced Photonics (IPR, NOMA, Sensors, Networks, SPPCom, PS), OSA Technical Digest (Optical Society of America), paper ITu1A.6, July 2017.
  84. A Saavedra, J. Pezoa, P. Zarkesh-Ha, and M. Figueroa, “An embedded system for face classification in infrared video using sparse representation,” Applications of Digital Image Processing XL, vol. 10396, page 103961N, Sept. 2017.
  85. N. H. Sule, T. Powell, S. Hemmady and P. Zarkesh-Ha, “Predicting the Tolerance of Extreme Electromagnetic Interference on MOSFETs,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, pp. 597-601, May 2018.
  86. T. Powell, N. H. Sule, S. Hemmady and P. Zarkesh-Ha, “Predictive Model for Extreme Electromagnetic Compatibility on CMOS Inverters,” International Symposium on Electromagnetic Compatibility (EMC EUROPE), Amsterdam, pp. 113-116, Sept. 2018.
  87. J. Trujillo, C. Merino, and P. Zarkesh-Ha, “SRAM Physically Unclonable Functions Implemented on Silicon Germanium,” IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, pp. 1-4, June 2019.
  88. Z. Abedi, S. Hemmady, T. Antonsen, E. Schamiloglu, and P. Zarkesh-Ha, “Electromagnetic Compatibility in Leakage Current of CMOS Integrated Circuits,” International Symposium on Electromagnetic Compatibility (EMC EUROPE), Barcelona, 2019, pp. 765-768, Sept. 2019.