IEEE Papers
- Information Leakage from FPGA Routing and Logic Elements. IEEE Link
(J) -- if it uses a microprocessor, than it would be relevant.
- Low-overhead Solutions For Preventing Information Leakage Due To Hardware Trojan Horses. IEEE Link
(S) -- Has zero references to RISC-V or microprocessors. I can envision doing some of this being done with a CPU though. Maybe
generate a malicious IP module doing some kind of ethernet snooping or instruction cache spying.
Simple test case where an FPGA design (on an Altera Cyclone) is constructed with a CPU and encryption module that are assumed to be an
IP block that feed their output to a CRC and zero padding module in sequence to their output destination. This output is fed into a
Network MAC module that is also assumed to be possibly compromised IP. Output from the MAC is fed back into a zero padding remover and
CRC check. If it fails, the data is not transmitted.
The Network MAC module will see the zero padding and assume that its valid space to inject its payload, this data will be seen on the
destination target when the zeros are attempted to be removed.
Definitely something that can be examined in the lab.
- An Anomaly Detection Model for RISC-V in Automotive Applications: A Domain-Specific Accelerator Perspective. IEEE Link
(S) -- This has some use and discussion of "hardware performance monitoring" counters. Might be useful if we need to start poking
around for perf data. Simulation of a RISC-V architecture on gem5 to test out a proposed neural net trained on the HPM counters and
data that controls an accelerator. Appears to use a Simba chiplet architecture to really drive the whole thing with the RISC-V being
used for general purpose compute and control.
Basically gives a nice hint to poking at the performance monitors in RISC-V. Also gives a roadmap for tech to do limited ML type
things on this hardware.
- FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism. IEEE Link
(S) -- Interesting fault injection results where some of the faults can be reasonably detected, but the "riscv_jump_stress_test"
seemed to miss 10%. Odd. Error/faults are injected into the system running on RISC-V, ARM CPUs and detected by having a paired
set of CPU cores executing instructions in sequence. When a comparator analyzes the output from either soft or hard fault
injection and detects a fault via their UVM framework. I’d need to really pull apart their process a bit as its not clear what
they injected and when. Its interesting that there is no explanation of the deviation in detection for the jump_stress_test in the
barchart.
- Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications. IEEE Link
(S) -- Kind of fun to see things you've taught us in extracting keys and on AES no less.. Defines some amount of resistance to
attacks with extra piplines and Dynamic Branch Prediction in the RISC-V cores. For myself, this is a very good paper introduction
to the area we are starting to investigate. Authors attach specific AES IP modules to a RISC-V on a FPGA and apply a power
attach (section 6) to extract the keys via MATLAB. A lot of good references for me to go investigate in this paper.
- EMAClave: An Efficient Memory Authentication for RISCV Enclaves. IEEE Link
(S) -- RISC-V enclave that claims resistance to replay, side-channel attacks. Bloom filter based defenses attached to a secure
enclave for key storage on RISC-V. This is done as opposed to just copying the ARM/X86/POWER modules over as they are too big
and too intensive. The authors add a Last Level Cache to the design to prevent cache side channel attacks. Authors use RV8
and MIBench to simulate the systems (not real hardware). Design is compared to a cache locking mechanism “Penglai”
https://penglai-enclave.systems/
- Early Assessment of the Fault Tolerance of Complex Digital Components From Virtual Platform Based Profiling. IEEE Link
-- TBD
Assorted Papers
- Development of a benchmark suite for large vector architectures into a Continuous Integration workflow. Direct Paper Link
-- TBD
- Carfield: An Open-Research Platform for Safety, Resilient and Predictable Systems. Direct Slides Link
-- TBD
Phoronix Articles
- RISC-V With Linux 6.18 Brings Support For MIPS Vendor Extensions. Phoronix Article
(J) -- The X280 that we have has a vector extension unit but that huge port is not connected to anything in the PL
implementation. It will eventually be connected to something off-board but not for a while.
- Linux 6.1.8 XCL Poison Injection Framework. Phoronix Article
(S) -- For future Sean to investigate.
Code or Projects
- Rocket Chip Design for VCU128. Github Project Link
(S)-- Spun up OpenSBI and uboot from this project. So far so good. Booted into a RISC-V uboot. Currently doing a linux build.
- Rocket Chip Design for ZedBoard. Github Project Link
-- TBD
- LowRisc design for ZedBoard. Github Project Link
-- TBD
- Ubuntu Releases for SIFive HiFive Unmatched. Canonical Download Link
-- TBD
- Self-hosted pretrained LLM models Medium blog post
-- (S)-- Don't even bother with this if you don't have a 16G NVidia board in the 2080 class or higher. Tested gpt-oss, llama3 and gemma for a reasonable coding assistant. The 64GB gemma models seem to be the right fit for a coding assistant. Unsure how training these will work as time goes on. Interesting to see how distribution of publically available pre-trained models already exists and is good enough for working on rando projects already.
- Vivado RISC-V RocketCore projects booting Linux Full hosting of linux on an FPGA Softcore
-- TBD
Legend
- (S) - Sean
- (J) - Dr. Plusquellic