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The labs are a major emphasis in
this course. Labs will be graded on Quality and Punctuality. Quality of
the lab consists of two parts -- Functionality and Content of the
report (50\% each). Therefore if you have a working circuit but don't
write a lab report you will only receive half credit. If you do not
have functionality, the lab score will be 0 even if a report is turned
in.
Punctuality will alter the overall score of the lab. If a lab is turned
in on time, the Quality score is unaltered. If the lab is late the
Quality score will be adjusted accordingly. (see below)
- Quality
- Functionality
(50% of Quality)
Many of the labs will involve construction and testing of digital
circuits. It is critical that each circuit works correctly to the
specifications given. You can not receive
credit on a circuit that does not work.
- Report Content
( 50% of quality)
Content refers to the lab report. You will gather an archive of
information in the lab experience. It is your responsibility to clearly
organize and document the contents of your lab experience.
Documentation of the design requires that you include EVERYTHING
related to your preparation, implementation and testing. This includes
but is not limited to: truth tables, state graphs, Karnaugh maps,
schematics, DO files, UCF files, waveforms, oscilloscope capture
screens, etc. Your lab documentation should include:
- Table of Contents
A listing of all files in your project with a few-sentence description
of each. The hierarchy of this table of contents should match the
hierarchy of your project.
- Purpose
Describe in your own words, the purpose of the lab.
- Specifications
Write any specifications thatwere given to you as part of the lab
description. Also include any assumption you made for your design.
- Preliminary Design
Describe any design steps that you needed to do to complete your design.
- Laboratory
Describe what happened and what you did.
- Discussion and
Anomalies
Describe what you learned. Also provide description of any
anomalies encountered in the
lab. These should be bugs in the CAD tools, VHDL problems,
hardware problems and bugs you found in your design.
- Files
All of the files created during the lab. These should include but
is not limited to: logic equations, truth tables, K-maps, circuit
diagrams, schematics, state diagrams, VHDL files, DO files, UCF files,
simulation results and block diagrams or sketches of your design.
- Punctuality
Timeliness is important to keep
the class on schedule. Turn in your report by the time of the deadline
(Monday following the lab) to avoid late penalties. You must submit a
Lab Report to receive a full Lab grade.
Late
- 50% off of lab report. (Note! One late lab will not significantly
alter the overall lab score for the course, many late labs will.)
Since we will be creating web pages for your lab reports, you will need
to structure them so that I can more easily find them. Before the
lab is due, you need to email me the location of your files and I will
download them. Please put each lab in a separate
folder,
like:
http://www.unm.edu/~mynetid/ece238/lab1
http://www.unm.edu/~mynetid/ece238/lab2
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