ECE 520/424 - VLSI Design: Spring 2026
University of New Mexico


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Announcements:

April 22: To help you preparing for the final exam, the answers to the practice final exams (Final_07 and Final_08) are posted here.
March31: As requested in class, I am posting the essential hotkeys for L-Edit here
March 20: There are few points about 2008 midterm exam solutions. In problem 2-a, use the definition for VOL to calculate its value. Connect the input to VDD and solve the circuit by considering that IDSn=IDSp. In problem 2-b, find the input and output capacitance similar to the method that we used in a normal CMOS inverter (even if M1 region of operation is not constant). Note that in the answers for Cout the source junction capacitance for M2 is missing. The correct answer should also include Keq2*(Cj2*As2+Cjsw2*Ps2). In problem 3-a, you just need to plug in the numbers in the equation given for S. In problem 3-b, you also just need to plug in the numbers in the equation given by the hint.
March 14: To help you preparing for the midterm exam, the answers to the practice midterm exams (Midterm_07 and Midterm_08) are posted here.
Feb. 17: Due to my unexpected travel, there will be no class on Tuesday Feb. 24. Also, there will be no office hours on Wednesday Feb. 25.
Feb. 11: Hint for homework #4 - Measurements 1& 4 give you the threshold voltage, VT0. From here, VT0 will help you to determine what Vmin is. Then use the VT0 and the data from measurements 1 & 5 to compute Gamma. Finally, use the VT0 and data from measurements 3 & 6 to calculate Lambda.
Feb. 4: The due date for Homework 3 was postponed to Feb. 17, 2026.
Jan. 20: First day of class. We will meet in classroom ECE 310.


Course Info:


Class: TU-TR 11:00AM-12:15PM, Room ECE-310, 3 credits
Course webpage: www.unm.edu/~pzarkesh/ECE520


Instructor:
 
Prof. Payman Zarkesh-Ha (pzarkesh@unm.edu)
Office hours: Wednesday 2:00-3:00PM, or by appointments
Office location: ECE 230B
Webpage: www.unm.edu/~pzarkesh


Teaching Assistant:
 
TBD (tbd)
Office hours: By appointment
Office location: By appointment


Course Description:
 
This course is intended to be an introduction to the design of very large scale integration (VLSI) circuits. Advanced topics includes: IC technology, CAD tools, layout, design rules, CMOS circuit characterization and performance estimation, standard cells and full custom designs, architectures for VLSI, timing, and testability. This is a project-oriented course. The main objective of this course is to provide the student with the capability of designing VLSI circuits.


Textbooks:
 
J. M. Rabaey, A. Chandrakasan and B. Nikolic, "Digital Integrated Circuits: A Design Perspective", 2nd edition, Prentice Hall, New York, NY, 2003 (primary).
J. P. Uyemura, "Physical Design of CMOS Integrated Circuits Using L-Edit", Thomson-Engineering, 1995
A. Chandrakasan, W. Bowhill, and F. Fox, "Design of High-Performance Microprocessor Circuits", IEEE Press, 2000


Grading Policy:
 
Homework:       25%
Project:             25%
Midterm exam: 25%
Final exam:      25%