Date |
Day |
Topic |
Reading/Coverage |
August 21
|
Mon |
Introduction
to Digital Electronics |
Handout |
August
23
|
Wed |
Basic
Circuits with Diodes |
1.1
- 1.8 |
August
28
|
Mon |
Basic
Solid State Physics |
2.1
- 2.3 |
August 30
|
Wed |
Physics
of
Semiconductor Diodes |
2.4
- 2.6 |
September 4
|
Mon |
Labor
Day
|
- |
September 6
|
Wed |
Physics
of
Semiconductor MOSFETs |
3.1 |
September 11
|
Mon |
MOSFET
I-V
Characteristics |
3.2 |
September
13
|
Wed |
Basic
Circuits with MOSFET |
Handout
|
September
18
|
Mon |
MOSFET
Threshold Voltage & Parasitic Capacitance |
Handout |
September 20
|
Wed |
PSPICE
Review
|
-
|
September
25
|
Mon |
MOSFET
Scaling Issues |
Handout
|
September
27 |
Wed |
Basic
Digital Circuits with MOSFETs |
Handout
|
October 2
|
Mon |
CMOS
Inverter VTC & ITC |
5.1
- 5.4 |
October 4
|
Wed |
CMOS
Inverter Noise Margin & Delay Model |
5.5 |
October 9
|
Mon |
CMOS
Inverter Power |
5.6 |
October 11
|
Wed |
Midterm
Exam #1 |
-
|
October
16
|
Mon |
CMOS
Inverter Short Circuit Power |
5.6 |
October
18
|
Wed |
CMOS
Inverter Leakage Power |
5.7 |
October
23
|
Mon |
Gate
Sizing (Inverter Chain)
|
5.8 |
October
25
|
Wed |
Interconnect
Modeling I |
4.1
- 4.2 |
October 30
|
Mon |
Interconnect
Modeling II |
4.3
- 4.4 |
November 1
|
Wed |
CMOS
Fabrication |
12.1
- 12.9 |
November 6
|
Mon |
Design
Rules & Basic Layout Techniques |
11.1
- 11.6 |
November 8
|
Wed |
Combinational
Logic:
NAND & NOR Gates
|
6.1
- 6.2
|
November 13
|
Mon |
Combinational
Logic: Transmission
Gates
|
6.3 |
November
15 |
Wed |
Logic
Design Style: Static Logic |
7.1
|
November 20
|
Mon |
Midterm
Exam #2 |
- |
November
22
|
Wed |
Logic
Design Style:
Dynamic & Damino Logics
|
7.2
- 7.3
|
November
27 |
Mon |
Sequential
Logic: D Flip-Flop |
8.1
- 8.4 |
November 29
|
Wed |
Timing
Analysis |
8.9 |
December 4 |
Mon |
SRAM
Memories |
9.1
- 9.3 |
December 6
|
Wed |
DRAM
&
FLASH Memories |
9.4
- 9.6 |
December 11
|
Mon |
Final
Exam (5:30-7:30PM) |
- |